Y. Pan, D. Li, M. Hamada, and A. Kosuge, “A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor,” in IEEE 30th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2025. (To be presented)
J. Shin, R. Sumikawa, D. Li, M. Hamada, and A. Kosuge, “A Via-Programming DNN Processor Fabrication toward 1/40 Mask Cost,” in IEEE International Solid-State Circuits Conference (ISSCC’25), Feb. 2025. (To be presented)
H. Huang, Y. Mitarai, M. Kawano, M. Hamada, and A. Kosuge, “Thermal Analysis and Design Guideline of Massive Orthogonal Stacking Assembly IC Cube (MOSAIC) With Bump Connection Enabling SoC-DRAM Direct Stacking,” in IEEE 75th Electronic Components and Technology Conference (ECTC), May 2025. (To be presented)
M. Kawano, Y. Mitarai, H. Hashimoto, T. Fukushima, H. Hosokawa, J. Fujikata, H. Kikuchi, M. Hamada, T. Kuroda and A. Kosuge, “Massive Orthogonal Stacking Assembly IC Cube (MOSAIC) With Inductive Coupling for Exascale Memory Applications,” in IEEE 75th Electronic Components and Technology Conference (ECTC), May 2025. (To be presented)