D2 Shin presented his work on a novel structured ASIC-based AI processor that achieves both low development cost and low power consumption at ISSCC 2025. Please check here.
D2 Shin presented his work on a novel structured ASIC-based AI processor that achieves both low development cost and low power consumption at ISSCC 2025. Please check here.
Pan presented his DNN processor design method at ASP-DAC 2025! His work received Special Feature Award. Please check here.
D2 Shin’s paper has been accepted to ISSCC. He will present his research on via-programmable neuroarray processor for low-cost low-power AI processors.
Dr. Kosuge’s article on the AI processor workshop organized by IEEE Solid-State Dircuits Directions in August 2024 is published in the Fall 2024 special issue of IEEE Solid-State Society Magazine. You can see from here!
Kawada-san who participated in our research group as an on-campus internship last year, gave an oral presentation at the international conference IEEE APC-CAS 2024. She presented an AI processor technology that enables low latency and low power feature extraction in general speech recognition AI functions.
Every year, Matsuo-Iwasawa Laboratory, Graduate School of Engineering, The University of Tokyo, organizes a Deep Learning Lecture Series for the general public. Prof. Kosuge was invited and gave a lecture titled “Semiconductor Ecosystem Supporting the Evolution of LLM.”. Details can be found Here.
At ESSERC 2024, our ex-member Dr. Shiba presented the results of his research on low-power AI processors. The method involves dynamically adjusting the operating range of the ADC in accordance with the neural network pruning ratio. A prototype SRAM-based compute in memory chip was fabricated with 28 nm CMOS process node by our selves. This is a joint research project with TSMC. Congratulations!
Our paper on low-power AI processors has been accepted to IEEE ESSERC (9/9~9/12, Belgium)!
Our Low-power AI Compute-in-Memory (CiM) paper has been accepted to IEEE Journal of the Electron Devices Society.
We presented the latest research results on area-saving AI processor at IEEE International Symposium on Circuits and Systems (ISCAS’24), Singapore. This technology adaptively switches between coarse- and fine-grain approximations of nonlinear functions, reducing the circuit area of nonlinear function processing by up to 93% while preventing accuracy degradation. Please see the photo.