New paper about 3D chip stacking and thermal analysis is accepted to IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT). You can see early access from here.
New paper about 3D chip stacking and thermal analysis is accepted to IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT). You can see early access from here.
The website about prospective students is now open. You can access from Here!
We visited Yonsei University on October 31st to co-host the TY Workshop, and visited KAIST on November 4th to hold the KTT Workshop. Click here for details
M2 Pan presented his work titled “Resource-Efficient Wired-Logic DNN Processor Using Mixed-Precision Quantization Strategy,” at ICCE-ASIA 2025. Please check here.
Prof. Kosuge’s web interview article on MIT Technology Review Japan.
Researcher Prof. Amano presented his work at APCCAS 2025. His work received the Bronze Poster Award! Please check here.
M2 Mitarai presented his work titled “A 16 Gb/s 48.9 fJ/b PVT-Tolerant Standard-Cell-Based Receiver for AC-Coupled Chiplet Interconnects,” at APCCAS 2025. Please check here.
M2 Mitarai presented his work titled “A 78% Area-Reduction in Edge-Coupled Inductive Coupling Link for Flexible Chip Assembly Using Oblong Coil,” at SSDM 2025. Please check here.
M2 Yu presented his work titled “A 29.71dB PSNR Integer-based Learned Image Compression Toward Resource Efficient FPGA Implementation” at IEICE Society Conference. Please check here.
Researcher Prof. Amano presented his work titled “An SoC Design and Fabrication Hands-On Educational Course Within One Week Using Structured ASIC” at ISCAS 2025. Please check here.
M2 Pan presented his work titled “An 83.7% Resource-Reduced Wired-Logic DNN Processor by Embedding Mixed-Precision Modules into Non-Linear Function LUTs” at ISCAS 2025. Please check here.
Dr. Kawano and D2 Huang presented their work at IEEE ECTC, which is the top internationa conference regarding 3D chip stacking and assembly. Here you can see the poster.