Researcher Prof. Amano presented his work titled “An SoC Design and Fabrication Hands-On Educational Course Within One Week Using Structured ASIC” at ISCAS 2025. Please check here.
Researcher Prof. Amano presented his work titled “An SoC Design and Fabrication Hands-On Educational Course Within One Week Using Structured ASIC” at ISCAS 2025. Please check here.
M2 Pan presented his work titled “An 83.7% Resource-Reduced Wired-Logic DNN Processor by Embedding Mixed-Precision Modules into Non-Linear Function LUTs” at ISCAS 2025. Please check here.
Dr. Kawano and D2 Huang presented their work at IEEE ECTC, which is the top internationa conference regarding 3D chip stacking and assembly. Here you can see the poster.
D2 Shin presented his work on a novel structured ASIC-based AI processor that achieves both low development cost and low power consumption at ISSCC 2025. Please check here.
Pan presented his DNN processor design method at ASP-DAC 2025! His work received Special Feature Award. Please check here.
D2 Shin’s paper has been accepted to ISSCC. He will present his research on via-programmable neuroarray processor for low-cost low-power AI processors.
Dr. Kosuge’s article on the AI processor workshop organized by IEEE Solid-State Dircuits Directions in August 2024 is published in the Fall 2024 special issue of IEEE Solid-State Society Magazine. You can see from here!
Kawada-san who participated in our research group as an on-campus internship last year, gave an oral presentation at the international conference IEEE APC-CAS 2024. She presented an AI processor technology that enables low latency and low power feature extraction in general speech recognition AI functions.
Every year, Matsuo-Iwasawa Laboratory, Graduate School of Engineering, The University of Tokyo, organizes a Deep Learning Lecture Series for the general public. Prof. Kosuge was invited and gave a lecture titled “Semiconductor Ecosystem Supporting the Evolution of LLM.”. Details can be found Here.
At ESSERC 2024, our ex-member Dr. Shiba presented the results of his research on low-power AI processors. The method involves dynamically adjusting the operating range of the ADC in accordance with the neural network pruning ratio. A prototype SRAM-based compute in memory chip was fabricated with 28 nm CMOS process node by our selves. This is a joint research project with TSMC. Congratulations!