Y. Pan, D. Li, M. Hamada, and A. Kosuge, “A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor,” in IEEE 30th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2025. (Selected for Special Feature Award!)
J. Shin, R. Sumikawa, D. Li, M. Hamada, and A. Kosuge, “A Via-Programming DNN Processor Fabrication toward 1/40 Mask Cost,” in IEEE International Solid-State Circuits Conference (ISSCC’25), Feb. 2025.
H. Amano, A. Kosuge, H. Sumi, N. Shimamoto, Y. Ochiai, Y. Inoue, T. Mogami, Y. Mita and M. Ikeda, “Can the Agile-chip platform carve out a niche between ASICs and FPGAs?” IEEE Symposium on Low Power and High Speed Chips and Systems, April 2025.
H. Huang, Y. Mitarai, M. Kawano, M. Hamada, and A. Kosuge, “Thermal Analysis and Design Guideline of Massive Orthogonal Stacking Assembly IC Cube (MOSAIC) With Bump Connection Enabling SoC-DRAM Direct Stacking,” in IEEE 75th Electronic Components and Technology Conference (ECTC), May 2025.
M. Kawano, Y. Mitarai, H. Hashimoto, T. Fukushima, H. Hosokawa, J. Fujikata, H. Kikuchi, M. Hamada, T. Kuroda and A. Kosuge, “Massive Orthogonal Stacking Assembly IC Cube (MOSAIC) With Inductive Coupling for Exascale Memory Applications,” in IEEE 75th Electronic Components and Technology Conference (ECTC), May 2025.
Y. Pan, M. Hamada, A. Kosuge, “A 83.7% Resource Reduced FPGA-Based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT” in IEEE International Circuits and Systems (ISCAS), May 2025.
H. Amano, A. Kosuge, H. Sumi, N. Shimamoto, Y. Ochiai, Y. Inoue, T. Mogami, Y. Mita, M. Ikeda, “An SoC Design and Fabrication Hands-On Educational Course Within One Week Using Structured ASIC” in IEEE International Circuits and Systems (ISCAS), May 2025.
A. Kosuge, “(Invited) Hardware and Software Co-Designed Neuron Array Processor for AI-IoT Applications,” in IEEE International Parallel and Distributed Processing Symposium (IPDPS), Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA), June 2025.