D. Li, T. Zhao, K. Kobayashi, A. Kosuge, M. Hamada, T. Kuroda, “Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions,” in IEEE International Symposium on Circuits and Systems (ISCAS), May, 2024.
Kota Shiba, Zhijie Zhan, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda, “A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC,” in IEEE European Solid-State Electronics Research Conference (ESSERC), Sep, 2024.
A. Kawada, K. Kobayashi, J. Shin, R. Sumikawa, M. Hamada, A. Kosuge, “A 250.3uW Versatile Sound Feature Extractor Using 1024-Point FFT 64-ch LogMel Filter in 40nm CMOS,” in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov., 2024.
Y. Pan, D. Li, M. Hamada, A. Kosuge, “A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor,” in IEEE 30th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2025. (To be presented)